1. George B. Adams III, Dharma P. Agrawal, and Howard Jay Siegel, “A Survey and Comparison of Fault-Tolerant Multistage Interconnection Networks,” in Interconnection Networks for High-Performance Parallel Computers, Isaac D. Scherson and Abdou S. Youssef, editors, IEEE Computer Society Press, IEEE Catalog No. EH0405-1, ISBN 0-8186-6197-6, pp. 654-667, 1994. (Reprinted from Computer, pp. 14-27, June 1987.)

2. L. Bhuyan, Q. Yang, and Dharma P. Agrawal, “Performance of Multiprocessor Interconnection Networks,” in Interconnection Networks for Multiprocessors and Multicomputers, Anujam Varma and C. S. Raghavendra, editors, IEEE Computer Society Press, IEEE Catalog No. 94EH0380-6, ISBN 0-8186-4972-2, pp. 392-404, 1994. (Reprinted from IEEE Computer, Vol. 22, No. 2, pp. 25-37, Feb. 1989.)

3. George B. Adams III, Dharma P. Agrawal, and Howard Jay Siegel, “A Survey and Comparison of Fault-Tolerant Multistage Interconnection Networks,” in Interconnection Networks for Multiprocessors and Multicomputers, Anujam Varma and C. S. Raghavendra, editors, IEEE Computer Society Press, IEEE Catalog No. 94EH0380-6, ISBN 0-8186-4972-2, pp. 329-342, 1994. (Reprinted from Computer, pp. 14-27, June 1987.)

4. L. N. Bhuyan and Dharma P. Agrawal, “Generalized Hypercube and Hyperbus Structures for a Network of Microcomputers,” in Interconnection Networks for Multiprocessors and Multicomputers, Anujam Varma and C. S. Raghavendra, editors, IEEE Computer Society Press, IEEE Catalog No. 94EH0380-6, ISBN 0-8186-4972-2, pp. 25-35, 1994. (Reprinted from IEEE Transactions on Computers, Vol. C-33, No. 4, pp. 323-333, April 1984.)

5. Dharma P. Agrawal, V. K. Janakiram, and G. C. Pathak, “Evaluating the Performance of Multicomputer Configurations,” translated into Japanese and reprinted in Nikkei Electronics Magazine, 10.20, No. 406, pp. 219-234, 1986.

6. Dharma P. Agrawal, V. K. Janakiram, and G. C. Pathak, “Evaluating the Performance of Multicomputer Configurations,” reprinted in Multi-Microprocessors, edited by A. Gupta and published by the IEEE Press, pp. 181-193, 1987.

7. Dharma P. Agrawal and T. R. N. Rao, “Modulo (2n +1) Arithmetic Logic,” in book Residue Number System Arithmetic: Modern Applications in Digital Signal Processing, by M. Soderstand, W. Jenkins, G. Julline, and F. Taylor, editors, IEEE Press, 1986.

8. Dharma P. Agrawal, “Testing and Fault Tolerance of Multistage Interconnection Networks,” in tutorial text on VLSI Testing and Validation Techniques, by H. K. Reghbati, editor, IEEE Computer Society Press, 1985.

9. Dharma P. Agrawal and J-S. Leu, “Dynamic Accessibility Testing and Path Length Optimization of Multistage Interconnection Networks,” in tutorial text on Interconnection Networks, by C. L. Wu and T. Y. Feng, editors, IEEE Computer Society Press, 1984.

TECHNICAL REPORTS

1. S. D. Rampal, D. S. Reeves, I. Viniotis, and Dharma P. Agrawal, “End-to-end QoS guarantees with Statistical Multiplexing in ATM Networks,” Technical Report TR 95/2, Center for Advanced Computation and Communication, North Carolina State University, Raleigh, Feb. 1995.

2. S. D. Rampal, Dharma P. Agrawal, and D. S. Reeves, “Processor Scheduling Algorithm for Minimizing buffer requirements for Multimedia Applications,” CCSP Technical report, North Carolina State University, TR 94/16, July 1994.

3. T. A. Dahlberg and Dharma P. Agrawal, “Dependability Evaluation of Large Systems with Dependent Failures using a Hierarchical Network Model,” TR 83.325, IBM, Charlotte, 115 pages.

4. Dharma P. Agrawal and R. Jain, “A Multiprocessor System for Dynamic Scene Analysis,” Report No. CSC-81-018, Computer Science Department, Wayne State University, Detroit.

5. Dharma P. Agrawal and T. Y. Feng, “A Study of Communication Processor Systems,” Tech report RADC-TR-79-310, Rome Air Development Center, 179 pages, Dec. 1979.

6. Dharma P. Agrawal and T. R. N. Rao, “Short Length Block Codes for Reliability Improvement of Massive Memories,” Tech. Report, CS-7709, Computer Science Department, Southern Methodist University, Dallas, Aug. 1977.

7. Dharma P. Agrawal and T. R. N. Rao, “On Multiple Operand Addition of Signed Binary Numbers,” Tech. Report, CS-7710, Computer Science Department, Southern Methodist University, Dallas, TX. Aug. 1977.

8. Dharma P. Agrawal and T. R. N. Rao, “Coding Techniques for Fault-tolerant and Extreme Reliability of Very Massive Memories,” Tech. Report, Computer Science Department, Southern Methodist University, Dallas, TX. Oct. 1976, 24 pages.