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Ohio Board of Regents Distinguished Professor Computer Science and Computer Engineering

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PAPERS AND REPORTS

 

PAST JOURNAL PUBLICATIONS AT UNIVERSITY OF CINCINNATI

  1. Carlos Cordeiro, Sachin Abhyankar, and Dharma P. Agrawal, “A Novel Energy Efficient Communication Architecture for Bluetooth Ad hoc Networks,” Ad Hoc Journal, special issue on PWC2003, Lecture Notes in Computer Science, Volume 2775, Pages 692 – 710, Sept. 2003.

  2. C. Cordeiro, D. P. Agrawal, and D. Sadok, “Piconet Interference Modeling and Performance Evaluation of Bluetooth MAC Protocol,” IEEE Transactions on Wireless Communications, Vol. 2, No. 6, pp. 1240-1246, Nov. 2003.

  3. Oh-Han Kang and Dharma P. Agrawal, “Scalable scheduling for symmetric multiprocessors (SMP),” Journal of Parallel and Distributed Computing, Vol. 63, No. 3, pp. 273-285, March 2003.

  4. J. Wang, Q-A. Zeng, and D. P. Agrawal, “Performance Analysis for Preemptive and Priority Reservation Handoff Scheme in Integrated Service Based Wireless Mobile Networks,” IEEE Transactions on Mobile Computing, Vol. 2, No. 1, pp. 65-75, Jan.-March 2003.

  5. L. Venkataraman and Dharma P. Agrawal, “Strategies for Enhancing Routing Security in Protocols for Mobile Ad hoc Networks,” Journal of Parallel and Distributed Computing, Special Issue on Mobile Ad Hoc Networking and Computing, Vol. 63, No. 2, pp. 214-227, Feb. 2003.

  6. Eric Schweitz and Dharma P. Agrawal, “A Parallelization Domain Oriented Multilevel Graph Partitioner,” IEEE Transactions on Computers, Vol. 51, No. 12, pp. 1435-1441, Dec. 2002.

  7. Arati Manjeshwar, Qing-An Zeng, and Dharma P. Agrawal, “An analytical model for information retrieval in wireless sensor networks using enhanced APTEEN protocol,” IEEE Transactions on Parallel and Distributed Systems, Vol. 13, No. 12, pp. 1290-1302, Dec.2002.

  8. Qing-an Zeng and Dharma P. Agrawal, “Modeling and Efficient Handling of Handoffs in Integrated Wireless Mobile Networks,” IEEE Transactions on Vehicular Technology, Vol. 51, No. 6, pp. 1469-1478, Nov. 2002.

PAST JOURNAL PUBLICATIONS AT NORTH CAROLINA STATE UNIVERSITY

  1. H. Park and Dharma P. Agrawal, “A Generic Design Methodology for Deadlock-Free Routing in Multicomputer Networks,” Journal of Parallel and Distributed Systems, Special Issue on Routing in Computer and Communication Systems,” Vol. 61, No. 9, pp. 1225-1248, Sept. 2001.

  2. J. Wu and Dharma P. Agrawal, “Guest Editors’ Introduction: Challenges in Designing Fault-Tolerant Routing in Networks,” IEEE Transactions on Parallel and Distributed Systems, Special Issue on Fault-Tolerant Routing, Vol. 10, No. 10, pp. 961-963, Oct. 1999.

  3. C. Chen, Dharma P. Agrawal, and J. R. Burke, “Hybrid Graph Based Networks for Multiprocessing,” International Journal of Telecommunication Systems, Special issue on High Performance Computing & Interconnection Networks, Vol. 10, pp. 107-134, 1998.

  4. S. Darbha and Dharma P. Agrawal, “Optimal Scheduling Algorithm for Distributed Memory Machines,” IEEE Transactions on Parallel and Distributed Systems, Vol. 9, No. 1, pp. 87-95, Jan. 1998.

  5. H. Park and Dharma P. Agrawal, “Efficient Deadlock-Free Wormhole Routing and Virtual Channel Reduction in Shuffle-Based Networks,” Journal of Parallel and Distributed Systems, Vol. 46, No. 2, pp. 148-159, Nov. 1997.

  6. S. Darbha and Dharma P. Agrawal, “A Task Duplication Based Scalable Scheduling Algorithm For Distributed Memory Systems,” Journal of Parallel and Distributed Systems, Vol. 46, No. 1, pp. 15-27, Oct. 1997.

  7. Sanjeev Kumar and Dharma P. Agrawal, “The Shared Buffer Direct Access (SBDA) ATM switch architecture for broadband networks,” International Journal of Computer Systems Science and Engineering (IJCSE), Vol. 12, No. 2, pp. 69-79., March 1997

  8. Santosh Pande and Dharma P. Agrawal, “Special Issue on Compilation Techniques for Distributed Memory Systems,” Journal of Parallel and Distributed Systems, Vol. 38, pp. 107-113, Nov. 1996.

  9. H. Park and Dharma P. Agrawal, “WICI: An Efficient Hybrid Routing Scheme for Scalable and Hierarchical Networks,” IEEE Transactions on Computers, Vol. 45, No. 11, pp. 1272-1281, Nov. 1996.

  10. Anup Kumar and Dharma P. Agrawal, “Parameters for System effectiveness evaluation of Distributed Systems,” IEEE Transactions on Computers, Vol. 45, No. 6, pp. 746-752, June 1996.

  11. T. Y. Chung, Dharma P. Agrawal, S. Rai, and T. J. Chung, “A comparative study of doubly-connected directed topologies for LANs and MANs,” NETWORKS, An International Journal, Wiley Publishing, Vol. 27 pp. 35-51, 1996.

  12. Santosh Pande and Dharma P. Agrawal, “Run time Issues in Program Partitioning on Distributed Memory Systems,” Concurrency: Practice and Experience, special issue on Scheduling, Vol. 7, No. 5, pp. 429-454, Aug. 1995.

  13. Anup Kumar and Dharma P. Agrawal, “Parameters for System effectiveness evaluation of Distributed Systems,” IEEE Transactions on Computers, Vol. 45, No. 6, pp. 746-752, June 1996.

  14. T. Y. Chung, Dharma P. Agrawal, S. Rai, and T. J. Chung, “A comparative study of doubly-connected directed topologies for LANs and MANs,” NETWORKS, An International Journal, Wiley Publishing, Vol. 27, pp. 35-51, 1996.

  15. O. H. Karam and Dharma P. Agrawal, “Shuffle Tree based Hierarchical Interconnection Networks,” American Mathematical Society, Special Issue on DIMACS, Workshop on Interconnection Networks and Mapping and Scheduling Parallel Computations, Rutgers, N. J., Vol. 21, pp. 251-265, 1995.

  16. Santosh Pande, Dharma P. Agrawal, and J. Mauney, “A Scalable Scheduling Method for Functional Parallelism on Distributed Memory Multiprocessor,” IEEE Transactions on Parallel and Distributed Systems, Vol. 6, No. 4, pp. 388-399, April 1995.

  17. J. C. Conrad and Dharma P. Agrawal, “Asynchronous Parallel Arc Consistency Algorithms on a Distributed Memory Machine,” Journal of Parallel and Distributed Computing, Vol. 24, No. 1, pp. 27-40, Jan. 1995.

  18. M. D. Meyer and Dharma P. Agrawal, “Vectorization of the DLMS Transversal Adaptive Filter,” IEEE Transactions on Signal Processing, Vol. 42, No. 11, pp. 3237-3240, Nov. 1994.

  19. C. Chen, Dharma P. Agrawal, and J. R. Burke, “Design and Analysis of a Class of Highly Scalable Hierarchical Networks: PdBCube,” Journal of Parallel and Distributed Computing, Special issue on Scalable Algorithms and Architectures, Vol. 22, No. 3, pp. 555-564, Sept. 1994.

  20. Sandeep Kumar and Dharma P. Agrawal, “A Class Based Framework for Re-use of Synchronization Code in Concurrent Object-Oriented Languages,” International Journal of Computers and their Applications, Vol. 1, No. 1, pp. 11-23, Aug. 1994.

  21. S. B. Shukla, and Dharma P. Agrawal, “On Mapping periodic real-time applications on Multicomputers,” IEEE Transactions on Parallel and Distributed Systems, Vol. 5, No. 7, July 1994, pp. 778-784.

  22. Santosh Pande, Dharma P. Agrawal, and J. Mauney, “A New Threshold Scheduling Strategy for SISAL Programs on Private Memory Machines,” Journal of Parallel and Distributed Processing, Academic Press, Vol. 21, No. 2, pp. 223-236, May 1994.

  23. T. Y. Chung, N. K. Sharma, and Dharma P. Agrawal, “Cost-performance tradeoffs in Manhattan Street Networks vs. 2-D Torus,” IEEE Transactions on Computers, Vol. 43, No. 2, pp. 240-243, Feb. 1994.

  24. C. Chen, Dharma P. Agrawal, and J. R. Burke, “dBCube: A New Class of Hierarchical Multiprocessor Networks and its Area Efficient Layout,” IEEE Transactions on Parallel and Distributed Systems, Vol. 4, No. 12, pp. 1332-1343, Dec. 1993.

  25. M. D. Meyer and Dharma P. Agrawal, “A high sampling rate delayed LMS filter architecture,” IEEE Transactions on Circuits and Systems-II, Analog and Digital Signal Processing, Vol. 40, No. 11, pp. 727-729, Nov. 1993.

  26. Dharma P. Agrawal and L. M. Patnaik, “Guest Editors’ Introduction to Performance of Supercomputers,” Special Issue, Journal of Parallel and Distributed Systems, Vol. 19, pp. 143-146, Nov. 1993.

  27. Anup Kumar and Dharma P. Agrawal, “A Generalized Algorithm for Evaluating Distributed Program Reliability,” IEEE Transactions on Reliability, Vol. 42, No. 3, pp. 416-426, Sept. 1993.

  28. T. Y. Chung and Dharma P. Agrawal, “Design and Analysis of Multidimensional Manhattan Street Networks,” IEEE Transactions on Communications, Vol. 41, No. 2, pp. 295-298, Feb. 1993.

  29. J. M. Conrad and Dharma P. Agrawal, “Simulation of Generic Multiprocessor Configurations for Asynchronous Algorithms,” International Journal on Computer Simulation, special issue on Multiprocessor Networks, Vol. 3, pp. 147-164, 1993.

  30. N. M. Kini, Anup Kumar, and Dharma P. Agrawal, “Quantitative Reliability Analysis of Redundant Multistage Interconnection Networks,” American Mathematical Society/ACM DIMACS, Volume 5 entitled “Reliability of Computer and Communication Networks,”, pp. 153-170, 1991.

  31. Anup Kumar, Dharma P. Agrawal, M. O. Mahgoub, and C. R. Green, “Impact of Network Unreliability on the performance degradation of a class of cluster-based Multiprocessors,” IEEE Transactions. on Reliability, Vol. 40, No. 1, pp. 39-44, April 1991.

  32. J. R. Burke, C. Chen, T. Y. Lee, and Dharma P. Agrawal, “Performance Analysis of Single Stage Interconnection Networks,” IEEE Transactions on Computers, Vol. 40, No. 3, pp. 357-365, March 1991.

  33. M. D. Meyer and Dharma P. Agrawal, “Adaptive Lattice Filter Implementations on Pipelined Multiprocessor Architectures,” IEEE Transactions on Communications, Vol. 38, No. 1, pp. 122-124, Jan. 1990.

  34. Sukil Kim, Dharma P. Agrawal, and R. J. Plemmons, “Recursive Least Squares Computation on Distributed Memory,” Journal of Parallel and Distributed Computing, Academic Press, Vol. 8, No. 1, pp. 80-88, Jan. 1990.

  35. J. Mauney, Dharma P. Agrawal, Y. Choe, E. A. Harcourt, Sukil Kim, and W. J. Staats, “Computational Models and Resource Allocation for Supercomputers,” Proceedings of the IEEE, Vol. 77, No. 12, pp. 1859-1874, Dec. 1989.

  36. Sukil Kim, Dharma P. Agrawal, J. S. Leu and J. Mauney, “Modeling Techniques in a Parallelizing Compiler for the B-HIVE Multicomputer System,” International Journal of High-Speed Computing, Vol. 1, No. 1, pp. 143-164, May 1989.

  37. C. G. Botting, S. Rai, and Dharma P. Agrawal, “Reliability Computation of Multistage Interconnection Networks,” IEEE Transactions on Reliability, Vol. R-39, No. 2, pp. 138-145, April 1989.

  38. S. Rai and Dharma P. Agrawal, “Guest Editors’ Introduction,” IEEE Transactions on Reliability, Special issue on Reliability of Parallel and Distributed Computing Networks, Vol. R-39, No. 2, pp. 2-4, April 1989.

  39. V. K. Janakiram, Dharma P. Agrawal and R. Mehrotra, “A Randomized Parallel Backtracking Algorithm,” IEEE Transactions on Computers, Special Issue on Parallel Algorithms, Vol. C-37, no. 12, pp. 1665-1676, Dec. 1988.

  40. Anup Kumar, S. Rai, and Dharma P. Agrawal, “On Computer Communication Network Reliability Under Program Execution Constraints,” IEEE Journal on Selected Areas in Communications, Vol. 6, no. 8, pp. 1393 - 1400, Oct. 1988.

  41. V. K. Janakiram, E. F. Gehringer, Dharma P. Agrawal and R. Mehrotra, “A Randomized Parallel branch-and-bound algorithm,” International Journal of Parallel Programming, Vol. 17, No. 3, pp. 277-301, 1988.

  42. Dharma P. Agrawal, S. C. Kim, and N. K. Swain, “Design of Non-Equivalent Multistage Interconnection Networks,” IEEE Transactions on Computers, Vol. C-37, No. 2, pp. 232-237, Feb. 1988.

  43. Dharma P. Agrawal and I. O. Mahgoub, “Analysis of a Class of Cluster-Based Multiprocessor Systems,” Journal of Information Sciences, special issue on Parallel Processing, Vol. 43, nos. 1 & 2, pp. 85-105, Oct. - Nov. 1987.

  44. S. A. Al-Arian and Dharma P. Agrawal, “Physical Failures and Fault Models of CMOS Circuits,” IEEE Transactions on Circuits and Systems, Vol. CAS-34, No. 3, pp. 269-279, March 1987.

  45. Dharma P. Agrawal and J-S. Leu, “Dynamic Accessibility Testing and Path Length Optimization of Multistage Interconnection Networks,” IEEE Transactions on Computers, Vol. C-34, No. 3, pp. 255-266, March 1985.

  46. L. N. Bhuyan and Dharma P. Agrawal, “Generalized Hypercube and Hyperbus Structures for a Network of Microcomputers,” IEEE Transactions on Computers, Vol. C-33, No. 4, pp. 323-333, April 1984.

  47. L. N. Bhuyan and Dharma P. Agrawal, “Design and Performance of Generalized Interconnection Networks,” IEEE Transactions on Computers, Vol. C-32, No. 12, pp. 1081-1090, Dec. 1983.

  48. Dharma P. Agrawal, “Graph Theoretic Analysis and Design of Multistage Interconnection Networks,” IEEE Transactions on Computers, Vol. C-32, No. 7, pp. 637-648, July 1983.

  49. L. N. Bhuyan and Dharma P. Agrawal, “Performance Analysis of FFT Algorithms on Multiprocessor Systems,” IEEE Transactions on Software Engineering, Vol. SE-9, No. 4, pp. 512-521, July 1983.

  50. Dharma P. Agrawal and T. R. N. Rao, “Introduction: Computer Arithmetic,” IEEE Transactions on Computers, special issue on Computer Arithmetic, Vol. C-32, No. 4, pp. 329-330, April 1983.

  51. Dharma P. Agrawal, and R. Jain, “A Pipelined Pseudoparallel System Architecture for Real Time Dynamic Scene Analysis,” IEEE Transactions on Computers, Vol. C-22, No. 10, pp. 952-962, Oct. 1982.

  52. L. N. Bhuyan and Dharma P. Agrawal, “On Generalized Binary Systems,” IEEE Transactions on Computers, Vol. C-31, No. 4, pp. 335-338, April 1982.

PAST JOURNAL PUBLICATIONS

  1. Dharma P. Agrawal, “Conference summary, 5th Symposium on Computer Arithmetic,” Journal of Digital Systems, Volume V, No. 3, pp 294-298, Fall 1981.

  2. Dharma P. Agrawal and K. K. Agrawal, “Efficient Sorting with CCD and Magnetic Bubble Memories,” IEEE Transactions on Computers, Vol. C-30, No. 2, pp. 153-157, Feb. 1981.

  3. D. D. Barlow and Dharma P. Agrawal, “Teaching Microcomputer Programming with Applications Oriented Problems,” IEEE Transactions on Education, Vol. E-24, No. 1, Feb. 1981.

  4. Dharma P. Agrawal and V. K. Agrawal, “On-Line Bus Fault Diagnosis in Microprocessor Systems,” Journal of Digital Systems, Vol. 4, No. 4, pp. 377-391, Winter 1980.

  5. Dharma P. Agrawal, “On Negabinary-binary Arithmetic Relationships and their hardware reciprocity,” IEEE Transactions on Computers, Vol. C-29, No. 11, pp. 1032-1035, Nov. 1980.

  6. M. A. Abidi and Dharma P. Agrawal “On Conflict-free Permutations in Multistage Interconnection Network,” Journal of Digital Systems, (Special issue on parallel processing), Vol. 4, No. 2, pp. 115-134, Summer 1980.

  7. Dharma P. Agrawal, “High Speed Arithmetic Arrays,” IEEE Transactions on Computers, Vol. C-28, pp. 215-224, March 1979.

  8. Dharma P. Agrawal, “Comments on ’A Fast Gray-to-Binary Code Conversion’,” Proceedings of the IEEE, Vol. C-28, pp. 215-224, March 1979.

  9. Dharma P. Agrawal and T. R. N. Rao, “On Multiple Operand Addition of Signed Binary Numbers,” IEEE Transactions on Computers, Vol. C-27, pp. 1068-1070, Nov. 1978.

  10. Dharma P. Agrawal and T. R. N. Rao, “Modulo 2n +1 Arithmetic Logic,” IEEE Journal on Electronic Circuits and Systems, Vol. 2, No. 6, pp. 186-188, Nov. 1978.

  11. Dharma P. Agrawal, “A Novel Technique for Computing Negabinary Squares,” IEEE Transactions on Computers, Vol. C-27, pp. 266-270, March 1978.

  12. Dharma P. Agrawal, “Comments on ’A Note on Base -2 Arithmetic Logic’,” IEEE Transactions on Computers, Vol. C-26, p. 511, May 1977.

  13. Dharma P. Agrawal, “Signed Modified Reflected Binary Code,” IEEE Transactions on Computers, Vol. C-25, No. 5, pp. 549-552, May 1976.

  14. Dharma P. Agrawal, “Arithmetic Algorithms in a Negative Base,” IEEE Transactions on Computers, Vol. C-24, No. 10, pp. 998-1000, Oct. 1975.

  15. Dharma P. Agrawal, “On Negabinary Division and Square-rooting,” Digital Processes, Vol. 1, No. 3, pp. 267-274, Autumn 1975.

  16. Dharma P. Agrawal, “Negabinary Parallel Counters,” Digital Processes, Vol. 1, No. 1, pp. 75-85, Spring 1975.

  17. Dharma P. Agrawal and H. Singh, “An Iterative Array for Multiplication and Division,” Journal of Institute of Electronics and Telecommunication Engineers, Vol. 21, No. 2, pp. 43-44, Feb. 1975.

  18. Dharma P. Agrawal, “Negabinary Complex Number Multiplier,” Electronics Letters, Vol. 10, No. 23, pp. 502-503, Nov. 14, 1974.

  19. Dharma P. Agrawal, “Negabinary Carry-look-ahead Adder and Fast Multiplier,” Electronics Letters, Vol. 10, No. 15, pp. 312-313, July 25, 1974.

  20. Dharma P. Agrawal, “Fast B. C. D. Multiplier,” Electronics Letters, Vol. 10, No. 12, pp. 237-238, June 13, 1974.

  21. A. K. Kamal, H. Singh, and Dharma P. Agrawal, “A Generalized Pipeline Array,” IEEE Transactions on Computers, Vol. C-23, No. 5, pp. 533-536, May 1974.

  22. Dharma P. Agrawal, “Fast B. C. D./Binary Adder/Subtractor,” Electronics Letters, Vol. 10, No. 8, pp. 122-123, April 18, 1974. A brief description of this paper published by ’Electronic Design Magazine’ under column “International Technology” in Vol. 22, No. 19, 13th September 1974, p. 180.

  23. Dharma P. Agrawal and M. Lal, “On Parameter Space Method for Control System Analysis and Design,” Journal of Institution of Telecommunication Engineers, Vol. 16, No. 7, pp. 539-540, 1970.

  24. Dharma P. Agrawal and M. Lal, “Analysis and Design of Sampled Data Systems with Time Lag Using Parameter Plane Method,” Journal of Institution of Engineers, Vol. 50, No. 5, Part ET-2, pp. 77-79, Jan. 1970.

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