QUEST II was a DARPA funded project studying the construction of parallel CAD tools for building the next generation parallel computers. There are several parts to the QUEST II project and this document describes only the activities related to parallel simulation. The parallel simulation effort is exploring the use of algorithms for the parallel simulation of digital systems described in the hardware description language VHDL. In particular, we are exploring the construction of a parallel VHDL simulator that uses the Time Warp optimistic synchronization strategy.
To provide high performance VHDL simulation capabilities suitable for supporting the construction of the next generation parallel processing platforms. The simulator must quickly port to emerging parallel platforms and deliver good performance across a variety of parallel platforms.
The parallel simulator will use the Time Warp optimistic synchronization strategy. The simulation kernel is being implemented in a two tiered approach with a VHDL simulation kernel (TyVIS) implemented on top of a Time Warp simulation kernel (WARPED). A frontend VHDL analyzer/code generator is being separately developed under the SAVANT project. New approaches for optimizing the VHDL simulation process from the RASSP formal semantics project will be employed.
The WARPED kernel includes a standard programming interface under which any simulation kernel can be implemented. Currently, two implementations exist, namely: a sequential kernel and a parallel (Time Warp) kernel. The parallel kernel implements numerous optimizations to Time Warp and is highly configurable. The parallel kernel also contains a number of dynamic parameter adjustment algorithms that allow the kernel to dynamically tune its runtime parameters for optimal performance in any platform. The MPI message passing interface is used to aid portability.