SAVANT: VHDL Analysis Tools
SAVANT: VHDL Analysis Tools
The SCRAM analyzer will accept as input, VHDL, VHDL-AMS (under development), or VHDL-2001 (under development), check for syntactic and static semantic correctness, and store the model in the intermediate form (IIR). The SCRAM parser is constructed as an LL(2) grammar and using the Purdue Compiler Construction Tool Set (PCCTS) parser generator. SCRAM is written in C++ using g++ 2.95 (or later versions) for development.
The intermediate forms are jointly developed with John Willis of FTL Systems, Inc. The intermediate form standard is called AIRE and includes definitions of two intermediates, a memory resident data structure called IIR and a machine-independent file data structure called FIR. SAVANT only provides support for the IIR intermediate; SAVANT uses VHDL for it's library/file format. The SAVANT implementation of IIR includes the following extensions:
The transmute method is a collection of derived classes that support rewriting of the IIR into a reduced form. For example, the transmute methods will rewrite a VHDL concurrent signal assignment into it's equivalent VHDL process statement. These classes produce a reduced form IIR against which back-end CAD tools can operate.
Output generation in the SAVANT software suite is supported by the collection of publisher classes. Two overloaded methods, publish_vhdl() and publish_cpp(), are defined for all nodes of the reduced IIR. The publish_vhdl() method simply regenerates VHDL from the internal IIR. The publish_cpp() method produces c++ simulation code to link with the TyVIS VHDL simulation kernel.
The ability of separating a VHDL description into separate independent libraries necessitate the existence of a library manager. As specified by the VHDL language reference manual (LRM) (chapter 11), parts of a VHDL description can be separately compiled into a library and accessed in other parts of the VHDL description. The library manager has been designed to take care of this functionality. It allows the user to create design libraries and helps the parser locate design libraries that are referenced in other VHDL descriptions.
The SAVANT project has been integrated
with UC's WARPED parallel simulation research
project and provides an end-to-end VHDL-to-batch simulation
capability. WARPED provides a general purpose discrete event simulation API
that can be executed in parallel or sequentially. Built on top of WARPED
is a VHDL simulation kernel called TyVIS that links
with the C++ code generated from SAVANT for batch sequential or parallel
simulation.
SAVANT Software
The main SAVANT web pages are now maintained at Clifton Labs.
